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Wafer breakage during high temperature processing is a multi-million dollar problem in semiconductor manufacturing lines, the prime cost being in loss of product during the time taken to stop the line, recover the broken wafer, clean and restart the affected tool. Although Chen et al. (2009, 2010) found a statistical correlation between wafer failure during processing and the geometry of the edge bevel shape, the prime origin of these failures appears to be cracks at the wafer edge associated with misaligned handling tools. Rather than rely on statistical approaches (Cook 2006; Brun and Melkote 2009), we have developed an X-ray diffraction imaging (XRDI) technique for assessing the probability that individual cracks will propagate (Tanner et al. 2012). This methodology underpins commercial XRDI products now on the market.

We have studied the different modes of wafer breakage from edge cracks artificially introduced into 200 mm diameter, (001) oriented, silicon wafers by 50N Vickers indentations located at \(90^\circ \), \(180^\circ \) and \(270^\circ \) with respect to the orientation notch and placed between 20 and \(120\,\upmu \hbox {m}\) from the bevel edge. Indentations were performed with a Mitutoyo AVK-C2 Hardness Tester (Garagorri et al. 2010). For loads below 50N and indents located typically 1mm from the bevel edge, four fold crack patterns resembling those described by Cook (2006) were observed. However, when the symmetry was broken by the proximity of the wafer edge break-out occurred predominantly on the wafer edge side of the indent, relaxing the strain and leaving one or more long cracks lying in the direction of the wafer centre. Provided that the crack length exceeded about 2 mm length and the indent was positioned within \(70 \, \upmu \hbox {m}\) of the bevel edge catastrophic fracture could occur in our rapid thermal annealing (RTA) system. The cracks were found to be good models of cracks introduced by damage associated with misaligned robotic handling tools.

The Si wafers used were dislocation-free silicon wafers purchased from Y Mart Inc, Palm Beach Gardens, Florida, USA. All wafers were within \(0.2^\circ \) of (100) orientation. The nominally defect-free, double side polished, p-type wafers had resistivity below 10 ohm mm, and were of thickness \(725 (\pm 25)\,\upmu \hbox {m}\). No edge defects were visible either under optical inspection or in XRDI images of the as-received wafers, which had been packed and shipped in standard cassettes.

Finite element modelling of the stresses with inclusion of plastic deformation revealed a very different stress distribution as a function of annealing time. During the heating sequence the stresses were in the same sense as that predicted by the purely elastic model in that the tangential stress at the wafer edge was compressive, keeping the crack closed. As creep is not included in the FE model, the plastic relaxation will here be fully developed prior to cooling. On cooling, as for the purely elastic simulation, the tangential stress at the edge switched sign (Fig. 6c), opening the crack. However, in contrast to the purely elastic simulation, with inclusion of plastic relaxation, the radial stress near the edge of the wafer did not switch from compressive to tensile (Fig. 6a). As the tensile radial stress responsible for the change in crack orientation is no longer present, the crack continues to propagate. Because the {111} planes have the lowest surface energy (Tanaka et al. 2006), cleavage on these planes occurs preferentially and the brittle crack opens on this plane, resulting in a single, linear, fracture of the wafer which projects into the \(\langle 110\rangle \) direction in the plane of the wafer (Figs. 1b, 5). As cooling continues, the radial strain begins to change to tensile (Gorostegui-Colinas 2012) but not uniformly (Fig. 6b). The asymmetry of the resulting stress distribution is due to the crystallographic symmetry of the available slip systems being superimposed on the asymmetry associated with the heating elements in the furnace, resulting in a quite complex variation in the resolved shear stress as a function of angle around the wafer (Garagorri et al. 2012). At this stage, the tangential stress at the wafer edge is also predicted to switch back to being compressive (Fig. 6d) but by this time, the wafer will have fractured.

Samuels and Roberts (1989) studied the fracture of silicon initiated from indents under four point bending. They observed that below a critical temperature \(\hbox {T}_{\mathrm{c}}\), failure was by brittle fracture while above \(\hbox {T}_{\mathrm{c}}\) the failure was by ductile plastic yielding. They demonstrated that \(\hbox {T}_{\mathrm{c}}\) is a function of lattice hardness (doping level) and strain rate, their measured activation energy of \(2.1 \pm 0.1\hbox {eV}\) being in excellent agreement with our value, quoted above. While we do have evidence of plastic deformation during the plateau annealing, we have no evidence of ductile plastic yielding and none of the fractures show associated slip bands. The only examples of slip band nucleation at crack tips during plateau annealing are in wafers that did not fracture and the cracks did not propagate. Brittle fracture normally occurs during wafer cooling and we note that the FE simulations show that the temperature at the wafer edge is always lower than that at the centre. The thermocouples, which are located away from the wafer edge, will always give a reading higher than that at the edge. The evidence suggests that fracture from the edge crack predominantly occurs in the brittle regime but that during the plateau, the macroscopic plastic deformation relaxes the stress. We note that, when plastic relaxation does not occur, and the crack propagation is almost tangential, the crack path is not smooth and at a microscopic level the brittle crack path probably changes rapidly between low energy planes.

The very different fracture geometries in damaged silicon wafers following high temperature annealing under spike and plateau conditions are attributed to the presence of plastic relaxation during the plateau dwell time. This attribution of plastic deformation relaxing the stresses and resulting in linear cracking along the low index direction during plateau annealing, during which the wafer is held at a high temperature for 60 s, is consistent with the averaged dislocation velocity of \(0.24\,(\pm 0.02)\,\hbox {mm s}^{-1}\) presented in Fig. 4. In practice, a significant time is needed for the slip to occur and relax the thermal stresses. The lack of plastic relaxation in the spike anneal process arises from the fact that the wafer is not held for sufficiently long in the plastic regime above the brittle-ductile transition for the dislocations to travel far during that time. 2b1af7f3a8

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